1. Field of the Invention
This invention is directed to computer circuitry, in general, and to an improved floating point processor with unique architecture which may perform square root, in particular.
2. Prior Art
In the prior art, there are many computing machines and systems available. Many of these systems utilize floating point processors therein to perform one or more arithmetic functions. These functions are the usual functions such as addition, subtraction, multiplication and/or division. Square root is usually not implemented in hardware. Instead, it is implemented in either firmware or software which has a significantly lower performance than an implementation in hardware. In the cases where square root is implemented in hardware the FPP circuitry is usually very complex and costly. The floating point processors operate on so-called floating point numbers which comprise a base number or mantissa as well as an exponent portion. In many cases, the floating point processor (FPP) is a limiting factor in the speed of operation of the computing machine or apparatus. That is, the computing machine can operate at a very high data rate or throughput rate while the FPP is generally slower.
In some prior art devices of this type, various techniques have been implemented in order to speed the operation of the FPP. For example, the so-called "skip-over zeros and ones" technique is used by shifting partial products rapidly when "strings of ones" or "strings of zeros" are detected. This technique is generally known to be much faster than the so-called digit-by-digit process and is especially useful in multiplication operations.
Moreover, in many of the existing FPP systems or devices, the operating speed is achieved as a tradeoff in terms of complexity and/or expensive components. However, it is highly desirable, and continuing investigations are underway in order, to provide FPP systems which can increase operating speed while reducing the complexity and expense of the circuitry.